![]() ![]() When a packet is received in a port, it starts its journey in the ingress pipeline. Scheduled Forwarding and Virtual Output Queues It requires fast communication between the ingress pipeline and its egress counterpart. But when packets are buffered in potentially dozens of ingress PFEs (Packet Forwarding Engines), we need a new mechanism to guarantee the forwarding efficiency. When the packets are stored in egress before transmission, it’s easy to classify them and apply different treatments with QoS policies. It reduces the footprint on the Printed Circuit Board (PCB)Įverything in technology is a trade-off, it creates other challenges.It reduces by half the memory requirement.Using an ingress-only deep buffer offers multiple advantages: The egress on-chip buffer is 12 MB (6 per core). ![]() The ingress off-chip buffer is 8 GB (shared).The ingress on-chip buffer is 32 MB (16 per core).To compare the different memory sizes, let’s take the Jericho2 NPU example: It doesn’t have the size nor the structure to perform Quality of Service (QoS) treatment. The small on-chip buffer on the egress pipeline can be used to store packets before they are sent to the interface and can only discriminate between high and low priority. This mechanism of queue eviction to an off-chip buffer and return to an on-chip buffer occurs dynamically as soon as a threshold is exceeded. This second memory type will be an HBM or DDR. It’s only when a queue is getting congested that packets are moved to the Delay Bandwidth Buffer (DBB) or “Off-Chip Buffer”. In normal traffic conditions, the packets are stored in the ingress On-Chip Buffer (OCB). Indeed, a small packet buffer is still present in the egress pipeline, but it’s a very shallow space compared to the very large High-Bandwidth Memory (HBM) used off-chip and reachable from the ingress pipeline. We talk about “ingress-only buffering model” but in all fairness, we should probably call it “ingress-mostly buffering”. Ingress-only BufferingĭNX ASICs used in ACX7000 Series are based on a pipeline design where the packet memory is present in the ingress part. The concept described here will be useful for all follow up articles on ACX7k platforms since these principles are common to all products in this family. In this article, we describe this packet buffering logic by following the life of a packet, and we introduce the concept of a Virtual Output Queue (VOQ). More details on the DNX options and their architecture has been covered in the first article of the series: That second case includes the DNX chipsets powering Juniper ACX Series. They propose different packet buffering approaches, performed in both ingress and egress datapaths (sometimes referred to as “2-stage buffering architecture”) or in the ingress pipeline only. Many Network Processing Unit (NPU) architectures are available on the market today. To understand the life of a packet in an ACX7000 Series router, you first need to understand the idea behind Virtual Output Queues. ![]()
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